Code Documentation

host.cli module

PDQ frontend.

Evaluates times and voltages, interpolates and uploads them.

usage: pdq [-h] [-s SERIAL] [-c CHANNEL] [-f FRAME] [-t TIMES] [-v VOLTAGES]
           [-o ORDER] [-a] [-k AUX_DAC] [-u DUMP] [-r] [-m] [-n] [-e] [-d]

Named Arguments

-s, –serial	device url [“hwgrep://”] Default: “hwgrep://”
-c, –channel	channel: 3*board_num+dac_num [0] Default: 0
-f, –frame	frame [0] Default: 0
-t, –times	sample times (s) [“np.arange(5)*1e-6”] Default: “np.arange(5)*1e-6”
-v, –voltages	sample voltages (V) [“(1-np.cos(t/t[-1]*2*np.pi))/2”] Default: “(1-np.cos(t/t[-1]*2*np.pi))/2”
-o, –order	interpolation (0: const, 1: lin, 2: quad, 3: cubic) [3] Default: 3
-a, –aux-miso	route MISO to AUX/F5 TTL output [False] Default: False
-k, –aux-dac	DAC channel OR mask to AUX/F5 TTL output [0x7] Default: 7
-u, –dump	dump to file [None]
-r, –reset	do reset before Default: False
-m, –multiplier
	100MHz clock [False] Default: False
-n, –disarm	disarm group [False] Default: False
-e, –free	software trigger [False] Default: False
-d, –debug	debug communications Default: False

host.cli.main(dev=None)

Test a PDQ stack.

Parse command line arguments, configures PDQ stack, interpolate the time/voltage data using a spline, generate a wavesynth program from the data and upload it to the specified channel. Then perform the desired arming/triggering/starting functions on the stack.

host.pdq module

class host.pdq.CRC(poly, data_width=8)

Generic and simple table driven CRC calculator.

This implementation is:

• MSB first data
• “un-reversed” full polynomial (i.e. starts with 0x1)
• no initial complement
• no final complement

Handle any variation on those details outside this class.

>>> r = CRC(0x1814141AB)(b"123456789")  # crc-32q
>>> assert r == 0x3010BF7F, hex(r)

class host.pdq.Channel(max_data, num_frames)

PDQ Channel.

num_frames

int – Number of frames supported.

max_data

int – Number of 16 bit data words per channel.

segments

list[Segment] – Segments added to this channel.

clear()

Remove all segments.

new_segment()

Create and attach a new Segment to this channel.

Returns:Segment

place()

Place segments contiguously.

Assign segment start addresses and determine length of data.

Returns:Amount of memory in use on this channel. Return type:addr (int)

serialize(entry=None)

Serialize the memory for this channel.

Places the segments contiguously in memory after the frame table. Allocates and assigns segment and frame table addresses. Serializes segment data and prepends frame address table.

Parameters:entry (list[Segment]) – See table(). Returns:Channel memory data. Return type:data (bytes)

table(entry=None)

Generate the frame address table.

Unused frame indices are assigned the zero address in the frame address table. This will cause the memory parser to remain in the frame address table until another frame is selected.

The frame entry segments can be any segments in the channel.

Parameters:entry (list[Segment]) – List of initial segments for each frame. If not specified, the first num_frames segments are used as frame entry points. Returns:Frame address table. Return type:table (bytes)

class host.pdq.PdqBase(num_boards=3, num_dacs=3, num_frames=32)

PDQ stack.

checksum

int – Running checksum of data written.

num_channels

int – Number of channels in this stack.

num_boards

int – Number of boards in this stack.

num_dacs

int – Number of DAC outputs per board.

num_frames

int – Number of frames supported.

channels

list[Channel] – List of Channel in this stack.

disable(**kwargs)

Disable the device.

enable(**kwargs)

Enable the device.

ping()

Ping method returning True. Required for ARTIQ remote controller.

program(program, channels=None)

Serialize a wavesynth program and write it to the channels in the stack.

The Channel targeted are cleared and each frame in the wavesynth program is appended to a fresh set of Segment of the channels. All segments are allocated, the frame address tale is generated, the channels are serialized and their memories are written.

Short single-cycle lines are prepended and appended to each frame to allow proper write interlocking and to assure that the memory reader can be reliably parked in the frame address table. The first line of each frame is mandatorily triggered.

Parameters:

• program (list) – Wavesynth program to serialize.
• channels (list[int]) – Channel indices to use. If unspecified, all channels are used.

program_segments(segments, data)

Append the wavesynth lines to the given segments.

Parameters:

• segments (list[Segment]) – List of Segment to append the lines to.
• data (list) – List of wavesynth lines.

set_checksum(crc=0, board=15)

Set/reset the checksum register.

Parameters:

• crc (int) – Checksum value to write.
• board (int) – Board to write to (0-0xe), 0xf for all boards.

set_config(reset=False, clk2x=False, enable=True, trigger=False, aux_miso=False, aux_dac=7, board=15)

Set the configuration register.

Parameters:

• reset (bool) – Reset the board. Memory is not reset. Self-clearing.
• clk2x (bool) – Enable the clock multiplier (100 MHz instead of 50 MHz)
• enable (bool) – Enable the channel data parsers and spline interpolators.
• trigger (bool) – Soft trigger. Logical or with the hardware trigger.
• aux_miso (bool) – Drive SPI MISO on the AUX/F5 ttl port of each board. If False, drive the masked logical or of the DAC channels’ aux data.
• aux_dac (int) – Mask for AUX/F5. Each bit represents one channel. AUX/F5 is: aux_miso ? spi_miso : (aux_dac & Cat(_.aux for _ in channels) != 0)
• board (int) – Board to write to (0-0xe), 0xf for all boards.

set_frame(frame, board=15)

Set the current frame.

Parameters:

• frame (int) – Frame to select.
• board (int) – Board to write to (0-0xe), 0xf for all boards.

write_mem(channel, data, start_addr=0)

Write to channel memory.

Parameters:

• channel (int) – Channel index to write to. Assumes every board in the stack has num_dacs DAC outputs.
• data (bytes) – Data to write to memory.
• start_addr (int) – Start address to write data to.

write_reg(board, adr, data)

Write to a configuration register.

Parameters:

• board (int) – Board to write to (0-0xe), 0xf for all boards.
• adr (int) – Register address to write to (0-3).
• data (int) – Data to write (1 byte)

class host.pdq.Segment

Serialize the lines for a single Segment.

max_time

int – Maximum duration of a line.

max_val

int – Maximum absolute value (scale) of the DAC output.

max_out

float – Output voltage at max_val. In Volt.

out_scale

float – Steps per Volt.

cordic_gain

float – CORDIC amplitude gain.

addr

int – Address assigned to this segment.

data

bytes – Serialized segment data.

bias(amplitude=[], **kwargs)

Append a bias line to this segment.

Parameters:

• amplitude (list[float]) – Amplitude coefficients in in Volts and increasing powers of 1/(2**shift*clock_period). Discrete time compensation will be applied.
• **kwargs – Passed to line().

dds(amplitude=[], phase=[], **kwargs)

Append a DDS line to this segment.

Parameters:

• amplitude (list[float]) – Amplitude coefficients in in Volts and increasing powers of 1/(2**shift*clock_period). Discrete time compensation and CORDIC gain compensation will be applied by this method.
• phase (list[float]) – Phase/frequency/chirp coefficients. phase[0] in turns, phase[1] in turns/clock_period, phase[2] in turns/(clock_period**2*2**shift).
• **kwargs – Passed to line().

line(typ, duration, data, trigger=False, silence=False, aux=False, shift=0, jump=False, clear=False, wait=False)

Append a line to this segment.

Parameters:

• typ (int) – Output module to target with this line.
• duration (int) – Duration of the line in units of clock_period*2**shift.
• data (bytes) – Opaque data for the output module.
• trigger (bool) – Wait for trigger assertion before executing this line.
• silence (bool) – Disable DAC clocks for the duration of this line.
• aux (bool) – Assert the AUX (F5 TTL) output during this line. The corresponding global AUX routing setting determines which channels control AUX.
• shift (int) – Duration and spline evolution exponent.
• jump (bool) – Return to the frame address table after this line.
• clear (bool) – Clear the DDS phase accumulator when starting to exectute this line.
• wait (bool) – Wait for trigger assertion before executing the next line.

static pack(widths, values)

Pack spline data.

Parameters:

• widths (list[int]) – Widths of values in multiples of 16 bits.
• values (list[int]) – Values to pack.

Returns:

Packed data.

Return type:

data (bytes)

host.pdq.discrete_compensate(c)

Compensate spline coefficients for discrete accumulators.

Given continuous-time b-spline coefficients, this function compensates for the effect of discrete time steps in the target devices.

The compensation is performed in-place.

gateware.pdq module

gateware.comm module

gateware.dac module

gateware.platform module

class gateware.platform.Platform

PDQ Platform.

• Xilinx Spartan 3A 500E in a PQ208 package.
• 50 MHz single ended input clock.
• Single FT245R USB parallel FIFO.
• Three 16 bit LVDS DACs.
• Several TTL control lines.

gateware.escape module

gateware.ft245r module

gateware.spi module